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1 ? 2001 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-6001/- october 2, 2001 2.5v multi-queue fifo (16 queues) 18 bit wide configuration 589,824 bits, 1,179,648 bits and 2,359,296 bits idt and the idt logo are registered trademarks of integrated device technology, inc commercial and industrial temperature ranges advance information idt72t51433 idt72t51443 idt72t51453 features: choose from among the following memory density options: idt72t51433 ? ? ? ? ? total available memory = 589,824 bits idt72t51443 ? ? ? ? ? total available memory = 1,179,648 bits idt72t51453 ? ? ? ? ? total available memory = 2,359,296 bits configurable from 1 to 16 queues queues may be configured at master reset from the pool of total available memory in blocks of 512 x 18 or 1,024 x 9 independent read and write access per queue user selectable i/o: 2.5v lvttl, 1.5v hstl, 1.8v ehstl user programmable via serial port default multi-queue device configurations -idt72t51433: 2,048 x 18 x 16q -idt72t51443: 4,096 x 18 x 16q -idt72t51453: 8,192 x 18 x 16q 100% bus utilization, read and write on every clock cycle 200 mhz high speed operation (5ns cycle time) 3.6ns access time echo read enable & echo read clock outputs individual, active queue flags ( ov , ff , pae , paf , pr ) 8 bit parallel flag status on both read and write ports shows pae and paf status of 8 queues direct or polled operation of flag status bus global bus matching - (all queues have same input bus width and output bus width) user selectable bus matching options: - x18in to x18out - x9in to x18out - x18in to x9out - x9in to x9out fwft mode of operation on read port partial reset, clears data in single queue expansion of up to 8 multi-queue devices in parallel is available power down input provides additional power savings in hstl and ehstl modes. jtag functionality (boundary scan) available in a 256-pin pbga, 1mm pitch, 17mm x 17mm high performance submicron cmos technology industrial temperature range (-40c to +85c) is available q0 q1 q2 qmax multi-queue fifo fstr wen paf ff wradd waden wclk paf n x9, x18 data in pae pae n x9, x18 data out oe ov write control d in q out 8 8 7 read control write flags read flags 6001 drw01 estr eren rdadd raden erclk 8 ren rclk data path flow diagram
2 commercial and industrial temperature ranges idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits description: the idt72t51433/72t51443/72t51453 multi-queue fifo device is a single chip within which anywhere between 1 and 16 discrete fifo queues can be setup. all queues within the device have a common data input bus, (write port) and a common data output bus, (read port). data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. data writes and reads can be performed at high speeds up to 200mhz, with access times of 3.6ns. data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. the device provides full flag and output valid flag status for the queue selected for write and read operations respectively. also a programmable almost full and programmable almost empty flag for each queue is provided. two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. when 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a polled or direct mode of bus operation provides the flag busses with all queues status. bus matching is available on this device, either port can be 9 bits or 18 bits wide. when bus matching is used the device ensures the logical transfer of data throughput in a little endian manner. the user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 16, the individual queue depths being independent of each other. the programmable flag positions are also user programmable. all programming is done via a dedicated serial port. if the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. both master reset and partial reset pins are provided on this device. a master reset latches in all configuration setup pins and must be performed before programming of the device can take place. a partial reset will reset the read and write pointers of an individual fifo queue, provided that the queue is selected on both the write port and read port at the time of partial reset. echo read enable, eren and echo read clock, erclk outputs are provided. these are outputs from the read port of the fifo that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the qn outputs and the data being received by the input device. data read from the read port is available on the output bus with respect to eren and erclk, this is very useful when data is being read at high speed. the multi-queue fifo has the capability of operating its io in either 2.5v lvttl, 1.5v hstl or 1.8v ehstl mode. the type of io is selected via the iosel input. the core supply voltage (v cc ) to the multi-queue is always 2.5v, however the output levels can be set independently via a separate supply, v ddq . the devices also provide additional power savings via a power down input. this input disables the write port data inputs when no write operations are required. a jtag test port is provided, here the multi-queue fifo has a fully functional boundary scan feature, compliant with ieee 1449.1 standard test access port and boundary scan architecture. see figure 1, multi-queue fifo block diagram for an outline of the functional blocks within the device.
3 idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges oe x9, x18 q out output register q 0 - q 17 wradd waden input demux wclk wen write control logic d in write pointers active q flags paf general flag monitor fstr paf n ff fsync paf reset logic serial multi-queue programming pae / paf offset tms tdi tdo tck trst fm iw ow prs mrs si so sclk seni rclk ren read control logic read pointers active q flags pae general flag monitor estr ov esync rdadd raden df fxo fxi exi exo 6001 drw02 x9, x18 7 8 8 id0 id1 id2 device id 3 bit jtag logic seno dfm mast pae upto 16 fifo queues 0.5 mbit 1.1 mbit 2.3 mbit dual port memory output mux d 0 - d 17 pae n 8 null-q erclk eren io level control & power down iosel vref pd figure 1. multi-queue block diagram
4 commercial and industrial temperature ranges idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits preliminary d14 a d13 d12 d10 q9 d7 q6 d4 q3 d1 id1 tck tdo q12 q14 q15 d15 b d16 d11 d9 q8 d6 q5 d3 q2 d0 id0 tms tdi q11 q13 dnc d17 c gnd d8 q7 d5 q4 d2 q1 trst q0 iosel id2 q10 q17 d vddq vddq vddq vddq vddq vddq vdd vdd vdd vdd q16 e vddq vddq vddq vddq vdd vdd vdd vdd gnd gnd f vddq vddq vdd vdd gnd gnd gnd gnd gnd gnd g vdd vdd vdd vdd gnd gnd gnd gnd gnd gnd h vdd vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd j null q vdd vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd pd k gnd vref vdd vdd vdd vdd gnd gnd gnd gnd gnd gnd gnd master fm si l dfm df vddq vddq vdd vdd gnd gnd gnd gnd gnd gnd iw ow seno m seni so vddq vddq vddq vddq vdd vdd vdd vdd gnd gnd oe rdadd0 rdadd1 wradd1 n wradd0 sclk vddq vddq vddq vddq vddq vddq vdd vdd vdd vdd rdadd2 rdadd3 rdadd4 wradd4 p wradd3 wradd2 waden pae 3 paf 3 pae 6 paf 6 pae 7 paf 7 pae ff ov rdadd5 rdadd6 rdadd7 wradd6 r wradd5 fsync fstr pae 2 paf 2 pae 5 paf 5 eren paf 4 erclk paf pr raden estr esync wradd7 t fxi fxo paf 0 pae 1 paf 1 pae 4 wen ren wclk rclk prs mrs pae 0 12 3 4 13 512 611 710 8 9 14 15 16 6001 drw03 a1 ball pad corner exo exi gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc dnc gnd pin configuration pbga (bb256-1, order code: bb) top view note: 1. dnc - do not connect.
5 idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges detailed description multi-queue structure the idt multi-queue fifo has a single data input port and single data output port with up to 16 fifo queues in parallel buffering between the two ports. the user can setup between 1 and 16 fifo queues within the device. these queues can be configured to utilize the total available memory, providing the user with full flexibility and ability to configure the queues to be various depths, independent of one another. memory organization/ allocation the memory is organized into what is known as blocks, each block being 512 x 18 or 1,024 x 9 bits. when the user is configuring the number of queues and individual queue sizes the user must allocate the memory to respective queues, in units of blocks, that is, a single queue can be made up from 0 to m blocks, where m is the total number of blocks available within a device. also the total size of any given queue must be in increments of 512 x 18 or 1,024 x 9. for the idt72t51433, idt72t51443 and idt72t51453 the total available memory is 64, 128 and 256 blocks respectively (a block being 512 x 18 or 1,024 x 9). if any port is configured for x18 bus width, a block size is 512 x 18. if both the write and read ports are configured for x9 bus width, a block size is 1,024 x 9. queues can be built from these blocks to make any size queue desired and any number of queues desired. bus widths the input port is common to all fifo queues within the device, as is the output port. the device provides the user with bus matching options such that the input port and output port can be either x9 or x18 bits wide, the read and write port widths being set independently of one another. because the ports are common to all queues the width of the queues is not individually set, so that the input width of all queues are equal and the output width of all queues are equal. writing to & reading from the multi-queue data being written into the device via the input port is directed to a discrete fifo queue via the write queue select address inputs. conversely, data being read from the device read port is read from a queue selected via the read queue select address inputs. data can be simultaneously written into and read from the same fifo queue or different fifo queues. once a queue is selected for data writes or reads, the writing and reading operation is performed in the same manner as a conventional idt synchronous fifos, utilizing clocks and enables, there is a single clock and enable per port. when a specific queue is addressed on the write port, data placed on the data inputs is written to that queue sequentially based on the rising edge of a write clock provided setup and hold times are met. conversely, data is read on to the output port after an access time from a rising edge on a read clock. the operation of the write port is comparable to the function of a conventional fifo operating in standard idt mode. write operations can be performed on the write port provided that the queue currently selected is not full, a full flag output provides status of the selected queue. the operation of the read port is comparable to the function of a conventional fifo operating in fwft mode. when a fifo queue is selected on the output port, the next word in that queue will automatically fall through to the output register. all subsequent words from that queue require an enabled read cycle. data cannot be read from a selected queue if that queue is empty, the read port provides an output valid flag indicating when data read out is valid. if the user switches to a queue that is empty, the last word from the previous queue will remain on the output register. as mentioned, the write port has a full flag, providing full status of the selected queue. along with the full flag a dedicated almost full flag is provided, this almost full flag is similar to the almost full flag of a conventional idt fifo. the device provides a user programmable almost full flag for all 16 fifo queues and when a respective queue is selected on the write port, the almost full flag provides status for that queue. conversely, the read port has an output valid flag, providing status of the data being read from the queue selected on the read port. as well as the output valid flag the device provides a dedicated almost empty flag. this almost empty flag is similar to the almost empty flag of a conventional idt fifo. the device provides a user programmable almost empty flag for all 16 fifo queues and when a respective queue is selected on the read port, the almost empty flag provides status for that queue. programmable flag busses in addition to these dedicated flags, full & almost full on the write port and output valid & almost empty on the read port, there are two flag status busses. an almost full flag status bus is provided, this bus is 8 bits wide. also, an almost empty flag status bus is provided, again this bus is 8 bits wide. the purpose of these flag busses is to provide the user with a means by which to monitor the data levels within fifo queues that may not be selected on the write or read port. as mentioned, the device provides almost full and almost empty registers (program- mable by the user) for each of the 16 fifo queues in the device. in the idt72t51433/72t51443/72t51453 multi-queue fifo device the user has the option of utilizing anywhere between 1 and 16 fifo queues, therefore the 8 bit flag status busses are multiplexed between the 16 queues, a flag bus can only provide status for 8 of the 16 queues at any moment, this is referred to as a sector, such that when the bus is providing status of queues 1 through 8, this is sector 1, when it is queues 9 through 16, this is sector 2. if less than 16 queues are setup in the device, there are still 2 sectors, such that in polled mode of operation the flag bus will still cycle through 2 sectors. if for example only 14 queues are setup, sector 1 will reflect status of queues 1 through 8. sector 2 will reflect the status of queues 9 through 14 on the least significant 6 bits, the most significant 2 bits of the flag bus are dont care. the flag busses are available in two user selectable modes of operation, polled or direct. when operating in polled mode a flag bus provides status of each sector sequentially, that is, on each rising edge of a clock the flag bus is updated to show the status of each sector in order. the rising edge of the write clock will update the almost full bus and a rising edge on the read clock will update the almost empty bus. the mode of operation is always the same for both the almost full and almost empty flag busses. when operating in direct mode, the sector on the flag bus is selected by the user. so the user can actually address the sector to be placed on the flag status busses, these flag busses operate independently of one another. addressing of the almost full flag bus is done via the write port and addressing of the almost empty flag bus is done via the read port. expansion expansion of multi-queue devices is also possible, up to 8 devices can be connected in a parallel fashion providing the possibility of both depth expansion or queue expansion. depth expansion means expanding the depths of individual queues. queue expansion means increasing the total number of queues available. depth expansion is possible by virtue of the fact that more memory blocks within a multi-queue device can be allocated to increase the depth of a queue. for example, depth expansion of 8 devices provides the possibility of 8 queues of 32k x 18 deep within the idt72t51433, 64k x 18 deep within the idt72t51443, and 128k x 18 deep within the idt72t51453, each
6 commercial and industrial temperature ranges idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits queue being setup within a single device utilizing all memory blocks available to produce a single queue. this is the deepest fifo queue that can setup within a device. for queue expansion a maximum number of 128 (8 x 16) queues may be setup. if less queues are setup, then more memory blocks will be available to increase queue depths if desired. when connecting multi-queue devices in expansion mode all respective input pins (data & control) and output pins (data & flags), should be connected together between individual devices.
7 idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges d[17:0] data input bus lvttl these are the 18 data input pins. data is written into the device via these input pins on the rising edge din input of wclk provided that wen is low. due to bus matching not all inputs may be used, any unused inputs should be tied low. df (1) default flag lvttl if the user requires default programming of the multi-queue device, this pin must be setup before master input reset and must not toggle during any device operation. the state of this input at master reset determines the value of the pae / paf flag offsets. if df is low the value is 8, if df is high the value is 128. dfm (1) default mode lvttl the multi-queue device requires programming after master reset. the user can do this serially via the input serial port, or the user can use the default method. if dfm is low at master reset then serial mode will be selected, if high then default mode is selected. erclk rclk echo hstl-lvttl read clock echo output, this output generates a clock based on the read clock input, this is used for output source synchronous clocking where the receiving devices utilizes the erclk to clock data output from the fifo. eren ren echo hstl-lvttl read enable echo output, can be used in conjunction with the erclk output to load data output from the output fifo into the receiving device. estr pae n flag bus lvttl if direct operation of the pae n bus has been selected, the estr input is used in conjunction with rclk strobe input and the rdadd bus to select a sector of queues to be placed on to the pae n bus outputs. a sector addressed via the rdadd bus is selected on the rising edge of rclk provided that estr is high. if polled operations has been selected, estr should be tied inactive, low. esync pae n bus sync lvttl esync is an output from the multi-queue device that provides a synchronizing pulse for the pae n bus output during polled operation of the pae n bus. during polled operation each sector of queue status flags is loaded on to the pae n bus outputs sequentially based on rclk. the first rclk rising edge loads sector 1 on to pae n, the second rclk rising edge loads sector 2. the third rclk rising edge will again load sector 1. during the rclk cycle that sector 1 of a selected device is placed on to the pae n bus, the esync output will be high. for sector 2 of that device, the esync output will be low. exi pae n bus lvttl the exi input is used when multi-queue devices are connected in expansion mode and polled pae n expansion in input bus operation has been selected . exi of device n connects directly to exo of device n-1. the exi receives a token from the previous device in a chain. in single device mode the exi input should be tied low if the pae n bus is operated in direct mode. if the pae n bus is operated in polled mode the exi input should be connected to the exo output of the same device. in expansion mode the exi of the first device should be tied low, when direct mode is selected. exo pae n bus lvttl exo is an output that is used when multi-queue devices are connected in expansion mode and polled expansion out output pae n bus operation has been selected . exo of device n connects directly to exi of device n+1. this pin pulses when device n has placed its 2nd sector on to the pae n bus with respect to rclk. this pulse (token) is then passed on to the next device in the chain n+1 and on the next rclk rising edge the first sector of device n+1 will be loaded on to the pae n bus. this continues through the chain and exo of the last device is then looped back to exi of the first device. the esync output of each device in the chain provides synchronization to the user of this looping event. ff full flag lvttl this pin provides the full flag output for the active fifo queue, that is, the queue selected on the input output port for write operations, (selected via wclk, wradd bus and waden). on the wclk cycle after a queue selection, this flag will show the status of the newly selected queue. data can be written to this queue on the next cycle provided ff is high. this flag has high-impedance capability, this is important during expansion of devices, when the ff flag output of up to 8 devices may be connected together on a common line. the device with a queue selected takes control of the ff bus, all other devices place their ff output into high-impedance. when a queue selection is made on the write port this output will switch from high-impedance control on the next wclk cycle. this flag is synchronized to wclk. fm (1) flag mode lvttl this pin is setup before a master reset and must not toggle during any device operation. the state of the input fm pin during master reset will determine whether the paf n and pae n flag busses operate in either polled or direct mode. if this pin is high the mode is polled, if low then it will be direct. fstr paf n flag bus lvttl if direct operation of the paf n bus has been selected, the fstr input is used in conjunction with wclk strobe input and the wradd bus to select a sector of queues to be placed on to the paf n bus outputs. a sector addressed via the wradd bus is selected on the rising edge of wclk provided that fstr is high. if polled operations has been selected, fstr should be tied inactive, low. pin descriptions symbol name i/o type description
8 commercial and industrial temperature ranges idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits pin descriptions (continued) fsync paf n bus sync lvttl fsync is an output from the multi-queue device that provides a synchronizing pulse for the paf n bus output during polled operation of the paf n bus. during polled operation each sector of queue status flags is loaded on to the paf n bus outputs sequentially based on wclk. the first wclk rising edge loads sector 1on to paf n, the second wclk rising edge loads sector 2. the third wclk rising edge will again load sector 1. during the wclk cycle that sector 1 of a selected device is placed on to the paf n bus, the fsync output will be high. for sector 2 of that device, the fsync output will be low. fxi paf n bus lvttl the fxi input is used when multi-queue devices are connected in expansion mode and polled paf n expansion in input bus operation has been selected. fxi of device n connects directly to fxo of device n-1. the fxi receives a token from the previous device in a chain. in single device mode the fxi input should be tied low if the pae n bus is operated in direct mode. if the pae n bus is operated in polled mode the fxi input should be connected to the fxo output of the same device. in expansion mode the fxi of the first device should be tied low, when direct mode is selected. fxo paf n bus lvttl fxo is an output that is used when multi-queue devices are connected in expansion mode and polled expansion out output paf n bus operation has been selected . fxo of device n connects directly to fxi of device n+1. this pin pulses when device n has placed its 2nd sector on to the paf n bus with respect to wclk. this pulse (token) is then passed on to the next device in the chain n+1 and on the next wclk rising edge the first sector of device n+1 will be loaded on to the paf n bus. this continues through the chain and fxo of the last device is then looped back to fxi of the first device. the fsync output of each device in the chain provides synchronization to the user of this looping event. id[2:0] (1) device id pins lvttl for the 16q multi-queue device the wradd and rdadd address busses are 8 bits wide. when a queue input selection takes place the 3 msbs of this 8 bit address bus are used to address the specific device (the 5 lsbs are used to address the queue within that device). during write/read operations the 3 msbs of the address are compared to the device id pins. the first device in a chain of multi-queues (connected in expansion mode), may be setup as 000, the second as 001 and so on through to device 8 which is 111, however the id does not have to match the device order. in single device mode these pins should be setup as 000 and the 3 msbs of the wradd and rdadd address busses should be tied low. the id[2:0] inputs setup a respective devices id during master reset. these id pins must not toggle during any device operation. note, the device selected as the master does not have to have the id of 000. iosel io select lvttl this pin is used to select either hstl or 2.5v lvttl operation for the i/o. if hstl or ehstl i/o are input required then iosel should be tied low. if lvttl i/o are required then it should be tied high. iw (1) input width lvttl iw selects the bus width for the data input bus. if iw is low during a master reset then the bus width input is x18, if high then it is x9. mast (1) master device lvttl the state of this input at master reset determines whether a given device (within a chain of devices), is the input master device or a slave. if this pin is high, the device is the master if it is low then it is a slave. the master device is the first to take control of all outputs after a master reset, all slave devices go to high-impedance, preventing bus contention. if a multi-queue device is being used in single device mode, this pin must be set high. mrs master reset lvttl a master reset is performed by taking mrs from high to low, to high. device programming is required input after master reset. null-q null queue select hstl-lvttl this pin is used on the read port when a null-q is required, it is used in conjunction with th e rdadd input address bus to address the null-q. oe output enable lvttl the output enable signal is an asynchronous signal used to providethree-state control of the multi-queue input data output bus, qout. if a devicehas been configured as a master device, the qout data outputs will be in alow impedance condition if the oe input is low. if oe is high then the qout data outputs will be in high impedance. if a device is configured a slave device, then the qout data outputs will always be in high impedance until that device has been selected on the read port, at which point oe provides three- state of that respective device. ov output valid flag lvttl this output flag provides output valid status for the data word present on the multi-queue fifo data output output port, qout. this flag is therefore, 2-stage delayed to match the data output path delay. that is, there is a 2 rclk cycle delay from the time a given queue is selected for reads, to the time the ov flag represents the data in that respective queue. when a selected queue on the read port is read to empty, the ov flag symbol name i/o type description
9 idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges ov output valid flag lvttl will go high, indicating that data on the output bus is not valid. the ov flag also has high-impedance (continued) output capability, required when multiple devices are used and the ov flags are tied together. ow (1) output width lvttl ow selects the bus width for the data output bus. if ow is low during a master reset then the bus width input is x18, if high then it is x9. pae programmable lvttl this pin provides the almost-empty flag status for the fifo queue that has been selected on the output almost-empty flag output port for read operations, (selected via rclk, rdadd and raden). this pin is low when the selected fifo queue almost-empty. this flag output may be duplicated on one of the pae n bus lines. this flag is synchronized to rclk. pae n programmable lvttl on the 16q device the pae n bus is 8 bits wide. at any one time this output bus provides pae status of almost-empty flag bus output 8 queues (1 sector), within a selected device, having a total of 2 sectors. during fifo read/write operations these outputs provide programmable empty flag status, in either direct or polled mode. the mode of flag operation is determined during master reset via the state of the fm input. this flag bus is capable of high-impedance state, this is important during expansion of multi-queue devices. during direct operation the pae n bus is updated to show the pae status of a sector of queues within a selected device. selection is made using rclk, estr and rdadd. during polled operation the pae n bus is loaded with the pae status of multi-queue fifo sectors sequentially based on the rising edge of rclk. paf programmable lvttl this pin provides the almost-full flag status for the fifo queue that has been selected on the input port almost-full flag output for write operations, (selected via wclk, wradd and waden). this pin is low when the selected fifo queue is almost-full. this flag output may be duplicated on one of the paf n bus lines. this flag is synchronized to wclk. paf n programmable lvttl on the 16q device the paf n bus is 8 bits wide. at any one time this output bus provides paf status of almost-full flag bus output 8 queues (1 sector), within a selected device, having a total of 2 sectors. during fifo read/write operations these outputs provide programmable full flag status, in either direct or polled mode. the mode of flag operation is determined during master reset via the state of the fm input. this flag bus is capable of high- impedance state, this is important during expansion of multi-queue devices. during direct operation the paf n bus is updated to show the paf status of a sector of queues within a selected device. selection is made using wclk, fstr, wradd and waden. during polled operation the paf n bus is loaded with the paf status of multi-queue fifo sectors sequentially based on the rising edge of wclk. pd power down hstl this input is used to provide additional power savings. when the device i/o is setup for hstl/ehstl input mode a high on the pd input disables the data inputs on the write port only, providing significant power savings. in lvttl mode this pin has no operation prs partial reset lvttl a partial reset can be performed on a single queue selected within the multi-queue device. before a partial input reset can be performed on a queue, that queue must be selected on both the write port and read port 2 clock cycles before the reset is performed. a partial reset is then performed by taking prs low for one wclk cycle and one rclk cycle. the partial reset will only reset the read and write pointers to the first memory location, none of the devices configuration will be changed. q[17:0] data output bus lvttl these are the 18 data output pins. data is read out of the device via these output pins on the rising edge qout output of rclk provided that ren is low, oe is low and the fifo queue is selected. due to bus matching not all outputs may be used, any unused outputs should not be connected. raden read address enable lvttl the raden input is used in conjunction with rclk and the rdadd address bus to select a queue to input be read from. a fifo queue addressed via the rdadd bus is selected on the rising edge of rclk provided that raden is high. raden cannot be high for the same rclk cycle as estr. rclk read clock lvttl when enabled by ren , the rising edge of rclk reads data from the selected fifo queue via the output input bus qout. the fifo queue to be read is selected via the rdadd address bus and a rising edge of rclk while raden is high. a rising edge of rclk in conjunction with estr and rdadd will also select the pae n flag sector to be placed on the pae n bus during direct flag operation. during polled flag operation the pae n bus is cycled with respect to rclk and the esync signal is synchronized to rclk. the pae and ov outputs are all synchronized to rclk. during device expansion the exo and exi signals are based on rclk. rclk must be continuous and free-running. rdadd read address bus lvttl for the 16q device the rdadd bus is 8 bits. the rdadd bus is a dual purpose address bus. the [7:0] input first function of rdadd is to select a fifo queue to be read from. the least significant 4 bits of the bus, pin descriptions (continued) symbol name i/o type description
10 commercial and industrial temperature ranges idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits pin descriptions (continued) symbol name i/o type description rdadd read address bus lvttl rdadd[3:0] are used to address 1 of 16 possible queues within a multi-queue device. address pin, [7:0] input rdadd[4] provides the user with a null-q address. if the user does not wish to address one of the 16 (continued) queues, a null-q can be addressed using this pin. the null-q operation is discussed in more detail later. the most significant 3 bits, rdadd[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. these 3 msbs will address a device with the matching id code. the address present on the rdadd bus will be selected on a rising edge of rclk provided that raden is high, (note, that data can be placed on to the qout bus, read from the previously selected fifo queue on this rclk edge). on the next rising rclk edge after a read queue select, a data word from the previous queue will be placed onto the outputs, qout, regardless of the ren input. two rclk rising edges after read queue select, data will be placed on to the qout outputs from the newly selected queue, regardless of ren due to the first word fall through effect. the second function of the rdadd bus is to select the sector of fifo queues to be loaded on to the pae n bus during strobed flag mode. the least significant bit, rdadd[0] is used to select the sector of a device to be placed on the pae n bus. the most significant 3 bits, rdadd[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. address bits rdadd[4:2] are dont care during sector selection. the sector address present on the rdadd bus will be selected on the rising edge of rclk provided that estr is high, (note, that data can be placed on to the qout bus, read from the previously selected fifo q on this rclk edge). please refer to table 2 for details on rdadd bus. ren read enable lvttl the ren input enables read operations from a selected fifo queue based on a rising edge of rclk. input a queue to be read from can be selected via rclk, raden and the rdadd address bus regardless of the state of ren . data from a newly selected queue will be available on the qout output bus on the second rclk cycle after queue selection regardless of ren due to the fwft operation. a read enable is not required to cycle the pae n bus (in polled mode) or to select the pae n sector , (in direct mode). sclk serial clock lvttl if serial programming of the multi-queue device has been selected during master reset, the sclk input input clocks the serial data through the multi-queue device. data setup on the si input is loaded into the device on the rising edge of sclk provided that seni is enabled, low. when expansion of devices is performed the sclk of all devices should be connected to the same source. seni serial input enable lvttl during serial programming of a multi-queue device, data loaded onto the si input will be clocked into t he input part (via a rising edge of sclk), provided the seni input of that device is low. if multiple devices are cascaded, the seni input should be connected to the seno output of the previous device. so when serial loading of a given device is complete, its seno output goes low, allowing the next device in the chain to be programmed ( seno will follow seni of a given device once that device is programmed). the seni input of the master device (or single device), should be controlled by the user. seno serial output enable lvttl this output is used to indicate that serial programming or default programming of the multi-queue device output has been completed. seno follows seni once programming of a device is complete. therefore, seno will go low after programming provided seni is low, once seni is taken high again, seno will also go high. when the seno output goes low, the device is ready to begin normal read/write operations. if multiple devices are cascaded and serial programming of the devices will be used, the seno output should be connected to the seni input of the next device in the chain. when serial programming of the first device is complete, seno will go low, thereby taking the seni input of the next device low and so on throughout the chain. when a given device in the chain is fully programmed the seno output essentially follows the seni input. the user should monitor the seno output of the final device in the chain. when this output goes low, serial loading of all devices has been completed. si serial in lvttl during serial programming this pin is loaded with the serial data that will configure the multi-queue devices. input data present on si will be loaded on a rising edge of sclk provided that seni is low. in expansion mode the serial data input is loaded into the first device in a chain. when that device is loaded and its seno has gone low, the data present on si will be directly output to the so output. the so pin of the first device connects to the si pin of the second and so on. the multi-queue device setup registers are shift registers. so serial out lvttl this output is used in expansion mode and allows serial data to be passed through devices in the chain output to complete programming of all devices. the si of a device connects to so of the previous device in the chain. the so of the final device in a chain should not be connected.
11 idt72t51433/72t51443/72t51453 2.5v, multi-queue fifo (16 queues) 18 bit wide configuration 589,824, 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges pin descriptions (continued) note: 1. inputs should not change after master reset. symbol name i/o type description tck jtag clock lvttl clock input for jtag function. tms and tdi are sampled on the rising edge of tck. tdo is output on input the falling edge of tck. tdi test data input lvttl during jtag boundary scan operation test data is serially loaded via tdi on the rising edge of tck. input this is also the data for the instruction register, jtag id register and bypass register. tdo test data output lvttl during jtag boundary scan operation test data is serially output via tdo on the falling edge of tck. input this output is in high-impedance except when shifting data while in shift-dr and shift-ir controller states. tms jtag mode select lvttl tms is a serial input pin. bits are serially loaded on the rising edge of tck, which selects 1 of 5 mod es input of operation for the jtag boundary scan. trst jtag reset lvttl trst is the asynchronous reset pin for the jtag controller. if the jtag port is not utilized, trst should input be tied to gnd. waden write address enable lvttl the waden input is used in conjunction with wclk and the wradd address bus to select a queue to input be written in to. a fifo queue addressed via the wradd bus is selected on the rising edge of wclk provided that waden is high. waden cannot be high for the same wclk cycle as fstr. wclk write clock lvttl when enabled by wen , the rising edge of wclk writes data into the selected fifo queue via the input input bus, din. the fifo queue to be written to is selected via the wradd address bus and a rising edge of wclk while waden is high. a rising edge of wclk in conjunction with fstr and wradd will also select the flag sector to be placed on the paf n bus during direct flag operation. during polled flag operation the paf n bus is cycled with respect to wclk and the fsync signal is synchronized to wclk. the paf n, paf and ff outputs are all synchronized to wclk. during device expansion the fxo and fxi signals are based on wclk. the wclk must be continuous and free-running. wen write enable lvttl the wen input enables write operations to a selected fifo queue based on a rising edge of wclk. input a queue to be written to can be selected via wclk, waden and the wradd address bus regardless of the state of wen . data present on din can be written to a newly selected queue on the second wclk cycle after queue selection provided that wen is low. a write enable is not required to cycle the paf n bus (in polled mode) or to select the paf n sector , (in direct mode). wradd write address bus lvttl for the 16q device the wradd bus is 7 bits. the wradd bus is a dual purpose address bus. the first [6:0] input function of wradd is to select a fifo queue to be written to. the least significant 4 bits of the bus, wradd[3:0] are used to address 1 of 16 possible queues within a multi-queue device. the most significant 3 bits, wradd[6:4] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. these 3 msbs will address a device with the matching id code. the address present on the wradd bus will be selected on a rising edge of wclk provided that waden is high, (note, that data present on the din bus can be written into the previously selected fifo queue on this wclk edge and on the next rising wclk also, providing that wen is low). two wclk rising edges after write queue select, data can be written into the newly selected queue. the second function of the wradd bus is to select the sector of fifo queues to be loaded on to the paf n bus during strobed flag mode. the least significant bit, wradd[0] is used to select the sector of a device to be placed on the paf n bus. the most significant 3 bits, wradd[6:4] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. address bits wradd[3:1] are dont care during sector selection. the sector address present on the wradd bus will be selected on the rising edge of wclk provided that fstr is high, (note, that data can be written into the previously selected fifo queue on this wclk edge). please refer to table 1 for details on the wradd bus. v cc +2.5v supply power these are v cc power supply pins and must all be connected to a +2.5v supply rail. v ddq o/p rail voltage power these pins must be tied to the desired output rail voltage. for lvttl i/o these pins must be connected to +2.5v, for hstl these pins must be connected to +1.5v and for ehstl these pins must be connected to +1.8v. gnd ground pin power these are ground pins and must all be connected to the gnd supply rail. vref reference voltage hstl this is a voltage reference input and must be connected to a voltage level determined from the table input "recommended dc operating conditions". the input provides the reference level for hstl/ehstl inputs. for lvttl i/o mode this input should be tied to gnd.
12 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: fifohelp@idt.com www.idt.com plastic ball grid array (pbga, bb256-1) low power 6001 drw34 l idt xxxxx device type x power xx speed x package x process / temperature range 72t51433 589,824 bits ? 2.5v multi-queue fifo 72t51443 1,179,648 bits ? 2.5v multi-queue fifo 72t51453 2,359,296 bits ? 2.5v multi-queue fifo bb commercial (0 c to +70 c) industrial (-40 c to +85 c) blank i (1) commercial only commercial & industrial commercial & industrial clock cycle time (t clk ) speed in nanoseconds 5 6 7-5 ordering information note: 1. industrial temperature range product for 6ns and 7-5ns speed grades are available as a standard device. all other speed grad es available by special order.

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